In large sampled analog systems, continuous analog signals are sampled at discrete intervals, which is be carefully chosen to ensure an accurate representation of the original analog signal. For example, prior to an analog-to-digital conversion, the analog signals may pass through some sort of signal conditioning circuitry which performs such functions as amplification, and attenuation, or filtering. If the analog signal originates, for example, as a temperature, pressure, flow rate or the like, then an appropriate sensor and transducer is required to first convert the physical quantity into an electrical voltage or current. A sampled analog circuit performs its calculations over a number of compute phases, with each phase executing a specific function, such as multiplication and addition. Multiple parallel systems may be used to concurrently sample input data and/or recombine their outputs to one or more post-processing circuits.
The phases of the sampled analog circuits on a chip must be synchronized, i.e. aligned, to enable the various analog circuits to cooperate reliably. Running all the analog circuits off a common master clock is difficult, in particular when the circuits and/or the chip have a large size, and even distributing the clock signal requires a not insignificant amount of power.
It would therefore be desirable and advantageous to obviate shortcomings and to provide an improved system and method for sampled analog clock distribution across large area chips, wherein the phases of different sampled analog circuits can be aligned precisely without requiring distribution of precisely clock aligned global clock pulses to and between the different analog circuits, while simultaneously significantly reducing the power demand of the SoC device.